Kaijie Wei

Project Assistant Professor, Keio University

FPT-EMS: An FPGA Implementation Using NB-LDPC Code for Continuous-Variable Quantum Key Distribution


Journal article


Kaijie Wei, Devanshu Garg, Ryutaro Nagai, Takao Tomono, Hideharu Amano
Heart, 2025

Semantic Scholar DBLP DOI
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APA   Click to copy
Wei, K., Garg, D., Nagai, R., Tomono, T., & Amano, H. (2025). FPT-EMS: An FPGA Implementation Using NB-LDPC Code for Continuous-Variable Quantum Key Distribution. Heart.


Chicago/Turabian   Click to copy
Wei, Kaijie, Devanshu Garg, Ryutaro Nagai, Takao Tomono, and Hideharu Amano. “FPT-EMS: An FPGA Implementation Using NB-LDPC Code for Continuous-Variable Quantum Key Distribution.” Heart (2025).


MLA   Click to copy
Wei, Kaijie, et al. “FPT-EMS: An FPGA Implementation Using NB-LDPC Code for Continuous-Variable Quantum Key Distribution.” Heart, 2025.


BibTeX   Click to copy

@article{kaijie2025a,
  title = {FPT-EMS: An FPGA Implementation Using NB-LDPC Code for Continuous-Variable Quantum Key Distribution},
  year = {2025},
  journal = {Heart},
  author = {Wei, Kaijie and Garg, Devanshu and Nagai, Ryutaro and Tomono, Takao and Amano, Hideharu}
}

Abstract

The Continuous-Variable Quantum Key Distribution (CV-QKD) is a groundbreaking technology that enables two parties, Alice and Bob, to share secret cryptographic keys with security guaranteed by the fundamental principle of quantum mechanics. The optical signal’s amplitude and phase quadratures are transmitted through a quantum channel and measured by the receiver (Bob). Due to channel noise, loss, and other imperfections, error correction is necessary to ensure both parties share identical raw key bits while minimizing information leakage to potential eavesdroppers (Eve). Non-Binary Low-Density Parity-Check (NB-LDPC) codes are well-suited for CV-QKD because they achieve high reconciliation efficiency, particularly in low-SNR scenarios. However, the intensive computational complexity hinders its further deployment in real-world applications. In this paper, we present an HLS-based decoder system, FPT-EMS (Field-Programmable T-EMS), which consists of six submodules aligning with the construction of the base design, Trellis-Based Extended Min-Sum (T-EMS). After the dedicated design of each submodule considering algorithm properties and FPGA characteristics, we ultimately achieved a 9.36 × speedup compared with ARM cores of the target platform, RFSoC 4x2, at the throughput of 0.89 Mbps over one iteration.


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