Abstract

With the explosion of data sets, classical computing can hardly meet the requirements for efficient data processing. Quantum computing with the capability of massively parallel processing is the key to next-generation computers. However, the state-of-the-art quantum computers still work at the ENIAC level due to the restricted qubits computation and unreliable results with noise. Quantum simulator provides a reliable environment for quantum algorithm designers, though the limited qubit scales induced by the exponential memory allocation $\left(2^{n+4}\right.$ bytes for the n-qubit quantum simulator). A simulator operating on over 40 qubits conventionally requires a high-spec platform like a supercomputer with enormous costs of manufacture, power consumption, etc. We propose a quantum simulator working on FPGA with extensible SATA storage named TREFOIL to overcome the constraints of memory shortage. Considering quantum gates’ data transfer pattern, we propose several HLS designs combined with HDL IPs’ interconnection to optimize the inefficiency of SATA data transfer. According to the result, the target designs simulate 35 qubits in approximately 4 to 7 minutes at less than $35 \mathrm{~W}$ in power consumption. Besides, we also present the extensibility of the entire system without significant performance degradation.