APA
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Mao, R., Wei, K., Amano, H., Kuno, Y., & Arai, M. (2021). Weight Least Square Filter for Improving the Quality of Depth Map on FPGA. 2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW).
Chicago/Turabian
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Mao, Renzhi, Kaijie Wei, H. Amano, Yukinori Kuno, and M. Arai. “Weight Least Square Filter for Improving the Quality of Depth Map on FPGA.” 2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW) (2021).
MLA
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Mao, Renzhi, et al. “Weight Least Square Filter for Improving the Quality of Depth Map on FPGA.” 2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW), 2021.
BibTeX Click to copy
@article{renzhi2021a,
title = {Weight Least Square Filter for Improving the Quality of Depth Map on FPGA},
year = {2021},
journal = {2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW)},
author = {Mao, Renzhi and Wei, Kaijie and Amano, H. and Kuno, Yukinori and Arai, M.}
}
The techniques based on measuring the distance between objects and the camera itself have made progress in recent years. Through this technology, the system used for 3D imaging will provide a great convenience for people’s lives. In this project, we focus on optimizing depth maps with better quality for the 3D scene display system on the car. During the 3D imaging process, to calculate the distance between a certain location and one of the specific points of the scene, it will produce two depth maps computed from two images as an intermediate product for 3D imaging processing. However, there is a great number of invalid pixels that distance cannot be measured. In dealing with such drawbacks, post-filtering has been introduced as a solution. In this project, we propose implementing the Weight Least Square (WLS) filter on FPGA, which can fill the invalid pixels by using the results of neighboring pixels. Through our approach, we can improve the quality of the depth map on M-KUBOS. Besides that, the optimized memory usage can successfully suit the size of the memory on-chip, and a 69.29% acceleration compared to the ARM core.