Journal article
Koki Honda, Kaijie Wei, H. Amano
International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019
International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019
Semantic Scholar
DBLP
DOI
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APA
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Honda, K., Wei, K., & Amano, H. (2019). FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board. International Symposium on Embedded Multicore/Many-Core Systems-on-Chip.
Chicago/Turabian
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Honda, Koki, Kaijie Wei, and H. Amano. “FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board.” International Symposium on Embedded Multicore/Many-core Systems-on-Chip (2019).
MLA
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Honda, Koki, et al. “FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board.” International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, 2019.
BibTeX Click to copy
@article{koki2019a,
title = {FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board},
year = {2019},
journal = {International Symposium on Embedded Multicore/Many-core Systems-on-Chip},
author = {Honda, Koki and Wei, Kaijie and Amano, H.}
}
Abstract
This paper presents the implementation of lane line detection on FPGA and Python. Lane line detection consists of three functions, median blur, adaptive threshold, and Hough transform. We implemented only accumulation of Hough transform on FPGA. Although the Hough transform cannot be implemented on a low-end FPGA board if implemented directly, by reducing ρθ space, it was successfully implemented on a low-end FPGA board. The rest of the Hough transform was implemented using Python's NumPy and SciPy, and OpenCV. Although it was very easy to write, it did not become a bottleneck for the whole process because of its effectiveness. As a result, we could achieve a 3.9x speedup compared to OpenCV and kept the developing cost down. When implementing median blur and adaptive threshold on an FPGA, we could achieve a 6.34x speedup.